CDP1852D3 데이터 시트보기 (PDF) - Intersil

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CDP1852D3

High-Reliability Byte-Wide Input/Output Port

Intersil 

CDP1852/3, CDP1852C/3

Dynamic Electrical Specifications Mode = 0 Input Port, See Figure 3, Input tr, tf ≤ 15ns; CL = 50pF (Continued)

LIMITS (NOTE 1)

-55oC, +25oC

+125oC

PARAMETER

SYMBOL

VDD

(NOTE 1)

VOLTS

MIN

MAX

(NOTE 1)

MIN

MAX

UNITS

Data-In After Clock Fall Hold Time

tDH

5

150

-

170

-

ns

10

70

-

100

-

ns

Propagation Delay Times:

Clear to SR

tRSR

5

10

-

200

-

340

ns

-

110

-

170

ns

Clock to SR

tCSR

5

10

-

175

-

220

ns

-

110

-

130

ns

Deselect to SR

tSSR

5

10

-

175

-

240

ns

-

110

-

120

ns

NOTE:

1. Time required by a device to allow for the indicated function.

(NOTE 1)

CS1 • CS2

tSW

CLOCK

DATA IN

DATA BUS

SR

tRSR

tWW

tDH

tDS

HIGH

IMPEDANCE

tCSR

tSSR

CLEAR

tCLR

NOTE:

1. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.

CLOCK

MODE = 0 TRUTH TABLE

CS1 • CS2 (Note 1)

CLEAR

DATA OUT EQUALS

SERVICE REQUEST

TRUTH TABLE

X

0

X

High Impedance

Clock =

CS1 or CS2 =

0

1

0

0

or CLEAR = 0

0

1

1

Data Latch

1

1

X

Data In

SR = 0

SR = 1

NOTE:

1. CS1 • CS2 = CS1 = 1, CS2 = 1.

FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

5

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