VP306SCGGP1N 데이터 시트보기 (PDF) - Mitel Networks

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VP306SCGGP1N

Satellite Channel Decoder

Mitel Networks 

DRAFT - PRELIMINARY DATA

VP305/6

FROM

LNB

SAW

SP5658

FREQ

SYNTH.

SL1710

LPF

I/Q DOWN

CONVERT

LPF

VCO 479.5MHz

/32

LOOP

FILTER

AGC

LOOP

FILTER

IIN

VP216/7

DUAL ADC

QIN

VCO

LOOP

FILTER

14.984375MHz

SYS_CLK

VP305/6

SYM_VCO

PSCAL

CR_VCO

AGC_OUT

MICROPROCESSOR

Fig. 2. System Application Diagram.

1.2. The QPSK Demodulator block.

The QPSK demodulator block performs the function of locking the receiver system to the incoming

data stream. It controls the voltage controlled oscillators (VCO) in the SL1710 I/Q down converter

and the VP216/7 dual analog to digital converter (ADC). The carrier frequency VCO is locked to

maintain the intermediate frequency (IF) of 479.5MHz. The symbol frequency VCO synthesiser

loop is locked to the twice the required symbol frequency (in the zero decimation case) and

generates the system clock SYS_CLK which is running at the bit rate.

SL1710

LPF

I/Q DOWN

CONVERT

LPF

/32 VCO

479.5MHz

LOOP

FILTER

IIN

VP216/7

DUAL ADC

QIN

VCO

LOOP

FILTER

14.984375MHz

SYS_CLK

SYM_VCO

XTI

CR_VCO

PSCAL

SYM_NF

SYM_RP

CR_RP

CR_U/LSWL

VP305/6

CONV

CONV

VCO

SWEEP

GEN

AFC

Fig. 3. Carrier and Symbol frequency synthesiser diagram.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

9

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