VP306SCGGP1N 데이터 시트보기 (PDF) - Mitel Networks

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VP306SCGGP1N

Satellite Channel Decoder

Mitel Networks 

DRAFT - PRELIMINARY DATA

VP305/6

2.6.4. SYM_RATIO: Symbol input decimation factor register. ...................................... 34

2.6.5. AGC_REF: Reference AGC level registers. ....................................................... 34

2.6.6. AGC_BW: AGC estimation bandwidth register................................................... 35

2.7. BANK 2: Program QPSK registers................................................................................ 36

2.7.1. SCALE: IOUT and QOUT outputs, scale factor register. .................................... 36

2.7.2. SNR_THS: Signal to noise ratio estimator threshold register. ............................ 36

2.7.3. CR_OFFSET: Carrier loop DC offset register..................................................... 37

2.7.3.1. Acquisition Phase. ................................................................................. 38

2.7.3.2. Tracking Phase...................................................................................... 39

2.7.4. CR_RP: Carrier reference period register........................................................... 39

2.7.5. CR_KP: Carrier loop filter gain (P term) register................................................. 40

2.7.6. CR_KD: Carrier loop filter gain (D term) register. ............................................... 40

2.7.7. CR_THSL: Carrier lock detector threshold register. ........................................... 41

2.8. BANK 3: Program QPSK registers................................................................................ 42

2.8.1. CR_SWR: Carrier sweep rate register................................................................ 42

2.8.2. CR_USWL U & L: Carrier Upper sweep limit registers....................................... 43

2.8.3. CR_LSWL U & L: Carrier Lower sweep limit registers. ...................................... 44

2.8.4. CR_CONFIG: Carrier configuration register. ...................................................... 44

2.8.5. CONFIG: Configuration register.......................................................................... 45

2.9. BANK 4: Monitor FEC read registers. ........................................................................... 46

2.9.1. VIT_ERR_C H & L: Viterbi error count registers................................................. 46

2.9.2. RS_UBC: Reed Solomon uncorrected block count register. .............................. 46

2.10. BANK 5: Program FEC registers. ................................................................................. 47

2.10.1. VIT_MODE: Viterbi mode register..................................................................... 47

2.10.2. VIT_ERR H, M & L: Viterbi error period registers. ............................................ 48

2.10.3. VI_MAX_ERR: Viterbi maximum bit error count register. ................................. 48

2.10.4. VI_BER_PER: Viterbi bit error rate based synchronisation period register. ..... 49

2.10.5. VI_BER_LIM: Viterbi bit error rate based synchronisation limit register. .......... 49

2.11. BANK 6: Program FEC and general control registers.................................................. 50

2.11.1. VIT_CTRL1: Viterbi control synchronisation byte register 1 ............................. 50

2.11.2. VIT_CTRL2: Viterbi control synchronisation byte register 2 ............................. 51

2.11.3. IE_FEC: Interrupt FEC register......................................................................... 52

2.11.4. STAT_EN: Status enable register..................................................................... 53

2.11.5. GEN_CTRL: General control register. .............................................................. 54

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

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