WED9LAPC2C16V8BC 데이터 시트보기 (PDF) - White Electronic Designs => Micro Semi

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WED9LAPC2C16V8BC

512K x 32 SSRAM / 1M x 64 SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs WED9LAPC2C16V8BC

SDRAM AC CHARACTERISTICS

Parameter

Symbol Min

Max

Units

Clock Cycle Time1

CL = 3

tCC

8

1000

ns

CL = 2

tCC

10

1000

ns

Clock to valid Output delay1,2

tSAC

6

ns

Output Data Hold Time2

tOH

2.5

ns

Clock HIGH Pulse Width3

tCH

3

ns

Clock LOW Pulse Width3

tCL

3

ns

Input Setup Time3

tSS

2

ns

Input Hold Time3

tSH

1

ns

CK to Output Low-Z2

tSLZ

1

ns

CK to Output High-Z

tSHZ

6

ns

Row Active to Row Active Delay4

tRRD

16

ns

RAS# to CAS# Delay4

tRCD

20

ns

Row Precharge Time4

tRP

20

ns

Row Active Time4

tRAS

48

10,000

ns

Row Cycle Time - Operation4

tRC

70

ns

Row Cycle Time - Auto Refresh4,8

tRFC

70

ns

Last Data in to New Column Address Delay5

tCDL

1

CK

Last Data in to Row Precharge5

tRDL

2

CK

Last Data in to Burst Stop5

tBDL

1

CK

Column Address to Column Address Delay6

tCCD

1

CK

Number of Valid Output Data7

2

ea

1

ea

NOTES:

1. Parameters depend on programmed CAS latency.

2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.

3. Assumed input rise and fall time = 1ns. If trise of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.

4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.

5. Minimum delay is required to complete write.

6. All devices allow every cycle column address changes.

7. In case of row precharge interrupt, auto precharge and read burst stop.

8. A new command may be given tRFC after self-refresh exit.

CLOCK FREQUENCY AND LATENCY PARAMETERS

(Unit = number of clock)

Cycle

Time

CAS

tRC

Latency 70ns

tRAS

48ns

tRP

20ns

tRRD

16ns

tRCD

20ns

tCCD

10ns

tCDL

10ns

tRDL

10ns

8.0ns

3

9

6

3

2

3

1

1

2

10.0ns

2

7

5

2

2

2

1

1

2

REFRESH CYCLE PARAMETERS

Parameter

Symbol

Min

Max Units

Refresh Period1,2

tREF

—

64

ms

NOTES:

1. 1024 cycles

2. Any time that the Refresh Period has been exceeded, a minimum of two

Auto (CBR) Refresh commands must be given to “wake-up” the device.

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

July, 2000

Rev. 0

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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