WED9LAPC2C16V8BC 데이터 시트보기 (PDF) - White Electronic Designs => Micro Semi

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WED9LAPC2C16V8BC

512K x 32 SSRAM / 1M x 64 SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs WED9LAPC2C16V8BC

SSRAM OPERATION TRUTH TABLE

Operation

WRITE Cycle, Begin Burst

READ Cycle, Begin Burst

READ Cycle, Begin Burst

Address Used

External

External

External

CWE#

L

H

H

COE#

X

L

H

CDATA

D

Q

High-Z

NOTE:

1. X means “don’t care”, H means logic HIGH. L means logic LOW.

2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to

HIGH) of SSCLK.

3. For a write operation following a read operation, SSOE# must be HIGH before the input data

required setup time plus High-Z time for SSOE# and staying HIGH thoughout the input data

hold time.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

FIG. 2 SSRAM READ TIMING

GCK

tKHKH

tKHKL

tKLKH

CADDR

tS

A1

A2

A3

A4

A5

tH

COE#

CWE#

CDATA

tOELQV

tOEHQZ

tKQLZ

tKHQX

tKHQV

Q(A1) Q(A2) Q(A3) Q(A4) Q(A5)

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

July, 2000

Rev. 0

4

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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