YGV627-V(2005) 데이터 시트보기 (PDF) - Yamaha Corporation

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YGV627-V
(Rev.:2005)

AVDP3E - Advanced Video Display processor 3 Enhanced

Yamaha Corporation 

YGV627

λ ENH ( I: PULL UP )

This signal permits enhanced functions for YGV617B.

When high level is inputted, only the registers that are compatible with YGV617B are made valid, and the

function of the enhanced registers are fixed to their default values. When low level is inputted, the function of the

enhanced register is made valid.

This pin selects enable / disable of the enhanced functions and determines SDRAM access timing at the same

time. In compatibility mode, the timing of access to SDRAM is equal to that of the performance of YGV617B, but

in enhancement mode, the access performance is doubled.

Since ENH is for selection of a mode, always fix it to either level.

< Video memory interface>

λ BA1−0, VA11−VA0 ( O )

These pins output address for SDRAM that is used as a video memory controlled by YGV627.

They output row address and column address on time sharing basis. BA1 and BA0 output bank address. However,

when VR64 is a high level input (16M bits SDRAM is connected), VA11 becomes bank select.

When a read command or write command is sent to the SDRAM, VA10 functions as auto-precharge enable.

Since these pins are always driven by YGV627, VRAM halt function of YGV617B cannot be used.

λ VD15−VD0 ( I/O: PULL UP )

These pins constitute a data bus for SDRAM that is used as video memory controlled by YGV627.

VRAM halt function of YGV617B cannot be used.

λ RAS ( O )

RAS outputs row address strobe signal for SDRAM that is used as a video memory controlled by YGV627.

Since RAS is always driven by YGV627, VRAM halt function of YGV617B cannot be used.

λ CAS ( O )

CAS outputs column address strobe signal for SDRAM that is used as a video memory controlled by YGV627.

Since CAS is always driven by YGV627, VRAM halt function of YGV617B cannot be used.

λ WE ( O )

WE outputs write strobe signal for SDRAM that is used as a video memory controlled by YGV627.

Since WE is always driven by YGV627, VRAM halt function of YGV617B cannot be used.

λ DQMH, DQML ( O )

These pins output data mask signal for SDRAM that is used as a video memory controlled by YGV627.

DQMH is for VD15 – VD8, and DQML is for VD7−VD0.

λ CS ( O )

This pin outputs chip select signal for SDRAM that is used as a video memory controlled by YGV627.

YGV627 requires connection to SDRAM because the device uses CS control for access to SDRAM for power

saving purpose and against switching noise.

λ SDCLK ( O )

This pin outputs clock for SDRAM that is used as a video memory controlled by YGV627.

Every output signal connected to SDRAM is outputted synchronizing with the rising edge of this clock. The read

data from SDRAM is latched in the YGV627 at the rising edge of this clock. The clock enable pin of SDRAM

should always be used in enable state.

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