YGV627-V(2005) 데이터 시트보기 (PDF) - Yamaha Corporation
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YGV627-V Datasheet PDF : 24 Pages
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YGV627
λ SYSEL ( I: PULL UP )
This signal selects the source of reference clock to be used in the system.
When low level is inputted to SYSEL, the system clock and dot clock use the same source of the clock. In this
case, the common clock is inputted into DTCKIN. Therefore, there is no need to input clock into SYCKIN. When
high level is inputted to SYSEL, SYCKIN pin input is used as the reference system clock independent from the dot
clock.
When SYSEL is used with low level input, be sure to input stable clock into DTCKIN even if the clock produced
by the built-in PLL is used as the dot clock. Since SYSEL is used for selection of a mode, always fix it to either
level. This pin has a pull-up resistor.
The function of this pin is the same as that of VCKS pin of YGV617B.
λ DTCKIN ( I ), DTCKOUT ( O )
Crystal is connected to these pins to input dot clock.
When operating the built-in PLL in FSC sync mode, the reference clock is inputted to these pins. At this time, the
clock with multiple of fsc is to be inputted. When PLL function is not used, this input clock is supplied directly to
the CRTC block and displays data control block. When low level is inputted to SYSEL, it is also supplied as the
reference system clock.
When inputted externally generated clock, input it into DTCKIN.
DTCKIN and DTCKOUT are the same as DCKIN and DCKOUT of YGV617B.
DTCKIN
DTCKOUT
λ DPLLVSSR, DPLLRREF, DPLLFILT ( Analog )
These pins are used to connect external resistors and capacitors for the built-in PLL that produces dot clock.
When directly using DTCKIN input signal as dot clock without using the built-in PLL, keep DPLLFILT open
and short-circuit between DPLLRREF and DPLLVSSR.
For the details of resistors and condensers value in the following figure, please refer to the Application Manual.
DPLLFILT
DPLLRREF
DPLLVSSR
Notes:
1. Arrange the components so that the parasitic capacitance among DPLLFILT, DPLLRREF and DPLLVSSR is
minimized and the signals do not cross each other.
2. PLL may not lock if there is a time difference between the rising moment of AVDD (for PLL) and the rising
moment of VDD (for Digital Logic).
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