AS7C33128PFS32A 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C33128PFS32A

3.3V 128K X 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

Key to switching waveforms

Rising input

®

Falling input

AS7C33128PFS32A

AS7C33128PFS36A

Undefined/don’t care

Timing waveform of read cycle

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

tCH

tADSPS

tADSPH

tADSCS

tADSCH

tAS

tAH

A1

A2

tWS

tWH

tCSS

tCSH

tCYC

tCL

LOAD NEW ADDRESS

A3

CE1

tADVS

tADVH

ADV

OE

DOUT

(pipelined mode) tOE

tLZOE

DOUT

(flow-through mode)

Q(A1)

Q(A1)

tHZOE

tOH

Q(A2)

Q(A2Ý01)

tCD

ADV INSERTS WAIT STATES

Q(A2Ý01)

Q(A2Ý10) Q(A2Ý11) Q(A3)

tHZC

Q(A3Ý01) Q(A3Ý10)

Q(A2Ý10)

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

tHZC

Note: Ý = XOR when LBO= HIGH/No Connect; Ý = ADD when LBO = LOW.

BW[a:d] is don’t care.

3/4/02; v.1.4

Alliance Semiconductor

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