BD3916FVM 데이터 시트보기 (PDF) - ROHM Semiconductor

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BD3916FVM

Positive and Negative Variable Linear Regulator

ROHM Semiconductor 

○BLOCK DIAGRAM

VCC 2

STB 6

BandGap

TSD

OCP

Discharge

Block

VEE 4

3/4

○PIN No.・PIN NAME

VCC

-

+

1 REG1

8 CTL1

7 GND

Pin No.

1

2

3

4

5

6

7

8

Pin Name

REG1

VCC

REG2

VEE

CTL2

STB

GND

CTL1

5 CTL2

3 REG2

+

-

VEE

※Refer to the Technical Note about the details of the application.

○OPERATING NOTES

1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result

in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage

is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where

the absolute maximum ratings may be exceeded is anticipated.

2) VEE potential

Ensure a minimum VEE pin potential in all operating conditions.

3) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating

conditions.

4) Pin short and mistake mounting

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result

in damage to the IC. Shorts between output pins and the power supply and GND pins caused by the presence of a foreign

object may result in damage to the IC. Ensure a minimum GND pin potential in all operating conditions.

5) Actions in strong magnetic field

Keep in mind that the IC may malfunction in strong magnetic fields.

6) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.

Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to

or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic

measure, and use similar caution when transporting or storing the IC.

7) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.

P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety

of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in the following

figure,

The P/N junction functions as a parasitic diode when VEE > Pin A for the resistor or VEE > Pin B for the transistor(NPN).

Similarly, when VEE > Pin B for the transistor (NPN), the parasitic diode described above combines with the N layer

of other adjacent elements to operate as a parasitic NPN transistor.

REV. C

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