MM74C373(2004) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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MM74C373
(Rev.:2004)
(Rev.:2004)
Fairchild Semiconductor
MM74C373 Datasheet PDF : 11 Pages
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AC Electrical Characteristics (Note 7)
MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0, tpd1
Propagation Delay,
CLOCK to Output
tSET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
tPWH, tPWL Minimum CLOCK Pulse Width
fMAX
Maximum CLOCK Frequency
t1H, t0H
tH1, tH0
tTHL, tTLH
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
tr, tf
CCLK
COD
Maximum CLOCK Rise
and Fall Time
Input Capacitance
Input Capacitance
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
tHOLD = 0 ns
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
RL = 10k, CL = 50 pF
VCC = 5V
VCC = 10V
RL = 10k, CL = 50 pF
VCC = 5V
VCC = 10V
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
VCC = 5V
VCC = 10V
CLOCK Input (Note 8)
OUTPUT DISABLE
Input (Note 8)
150
300
65
130
180
360
80
160
70
140
35
70
70
140
50
100
3.5
7.0
5
10
105
210
60
120
105
210
45
90
65
130
35
70
110
220
70
140
15
>2000
5
>2000
7.5
10
7.5
10
ns
ns
ns
MHz
ns
ns
ns
µs
pF
pF
CIN
COUT
Input Capacitance
Output Capacitance
Any Other Input (Note 8)
High Impedance
State (Note 8)
5
7.5
pF
10
15
pF
CPD
Power Dissipation Capacitance
Per Package (Note 9)
Note 7: AC Parameters are guaranteed by DC correlated testing.
250
pF
Note 8: Capacitance is guaranteed by periodic testing.
Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
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