MM74C373(2004) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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MM74C373
(Rev.:2004)
(Rev.:2004)
Fairchild Semiconductor
MM74C373 Datasheet PDF : 11 Pages
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AC Electrical Characteristics (Note 4)
MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0, tpd1
Propagation Delay,
LATCH ENABLE to Output
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
165
330
70
140
ns
195
390
85
170
tpd0, tpd1
Propagation Delay Data
In to Output
tSET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
LATCH ENABLE = VCC
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
tHOLD = 0 ns
VCC = 5V
VCC = 10V
155
310
70
140
ns
185
370
85
170
70
140
ns
35
70
fMAX
Maximum LATCH ENABLE
Frequency
VCC = 5V
VCC = 10V
3.5
6.7
4.5
9.0
MHz
tPWH
Minimum LATCH ENABLE
Pulse Width
VCC 5V
VCC = 10V
75
150
ns
55
110
tr, tf
t1H, t0H
tH1, tH0
tTHL, tTLH
Maximum LATCH ENABLE
Rise and Fall Time
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
VCC = 5V
VCC = 10V
RL = 10k, CL = 5 pF
VCC = 5V
VCC = 10V
RL = 10k, CL = 50 pF
VCC = 5V
VCC = 10V
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
NA
µs
NA
105
210
ns
60
120
105
210
ns
45
90
65
130
35
70
ns
110
220
70
140
CLE
Input Capacitance
COD
Input Capacitance
LE Input (Note 5)
OUTPUT DISABLE
Input (Note 5)
7.5
10
pF
7.5
10
pF
CIN
COUT
Input Capacitance
Output Capacitance
Any Other Input (Note 5)
High Impedance
State (Note 5)
5
7.5
pF
10
15
pF
CPD
Power Dissipation Capacitance
Per Package (Note 6)
Note 4: AC Parameters are guaranteed by DC correlated testing.
200
pF
Note 5: Capacitance is guaranteed by periodic testing.
Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
5
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