MAX126ACAX 데이터 시트보기 (PDF) - Maxim Integrated
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MAX126ACAX Datasheet PDF : 16 Pages
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2x4-Channel, Simultaneous-Sampling
14-Bit DAS
______________________________________________________________Pin Description
PIN
1, 2
3, 4
5
6
7
8, 36
9–16
17
18
19, 20
21–24
25
26
27
28
29
30
31
32, 33
34, 35
NAME
CH2B, CH2A
CH1B, CH1A
AVDD
REFIN
REFOUT
AGND
D13–D6
DVDD
DGND
D5, D4
D3/A3–D0/A0
CLK
CS
WR
RD
CONVST
INT
AVSS
CH4A, CH4B
CH3A, CH3B
FUNCTION
Channel 2 Multiplexed Inputs, single-ended
Channel 1 Multiplexed Inputs, single-ended
+5V ±5% Analog Supply Voltage
External Reference Input/Internal Reference Output. Bypass with a 0.1µF capacitor to AGND.
Reference-Buffer Output. Bypass with a 4.7µF capacitor to AGND.
Analog Ground. Both pins must be tied to ground.
Data Bits. D13 = MSB.
+5V ±5% Digital Supply Voltage
Digital Ground
Data Bits
Bidirectional Data Bits/Address Bits. D0/A0 = LSB.
Clock Input (duty cycle must be 30% to 70%).
Chip-Select Input (active-low)
Write Input (active-low)
Read Input (active-low)
Conversion-Start Input. Rising edge initiates sampling and conversion sequence.
Interrupt Output. Falling edge indicates the end of a conversion sequence.
-5V ±5% Analog Supply Voltage
Channel 4 Multiplexed Inputs, single-ended
Channel 3 Multiplexed Inputs, single-ended
_______________Detailed Description
The MAX125/MAX126 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
14-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX125/MAX126 internal micro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (see Figure 2).
The conversion timing and control sequences are
derived from a 16MHz external clock, the CONVST
1.6mA
TO OUTPUT
PIN
120pF
1.6V
1.0mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
6 _______________________________________________________________________________________
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