AS7C3364PFS32B 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C3364PFS32B

3.3V 64K X 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

AS7C3364PFS32B

AS7C3364PFS36B

®

Key to switching waveforms

Rising input

Falling input

don’t care

Timing waveform of read cycle

CLK

tADSPS

ADSP

tADSPH

tCYC

tCH

tCL

ADSC

tADSCS

tADSCH

tAS

tAH

Address

A1

A2

LOAD NEW ADDRESS

A3

GWE, BWE

tWS

tWH

tCSS

CE0, CE2

tCSH

Undefined

CE1

ADV

OE

Dout

tADVS

tADVH

ADV inserts wait states

tOE

tLZOE

Q(A1)

tHZOEtOH

Q(A2)

tCD

Q(A2Ý01)

Q(A2Ý10)

tHZC

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10)

Read

Q(A1)

Suspend

Read

Q(A1)

Read Burst Burst Suspend Burst Read Burst

Burst

Burst

Q(A2) Read Read

Read

Read Q(A3) Read

Read

Read DSEL

Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11)

Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

12/10/04; v.1.4

Alliance Semiconductor

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