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AM79C850KCW

SUPERNET® 3

Advanced Micro Devices 

AMD

PRELIMINARY

configurations with an external physical layer

controller.

s SUPERNET 3 has a Test Access Port and

Boundary Scan Architecture, IEEE1149.1.

s SUPERNET 3 provides Built-in Self Test (BIST)

features for the Address Filter, and PLC-S.

s All registers are readable and writable by the Node

Processor. All reserved bits shall be read back as

zero except where noted.

s The Receive Status (RS) pins are expanded from

5 to 6 pins to support enhanced status reporting.

s The Transmit Status (XS) pins are expanded from

3 to 4 pins to support enhanced status reporting.

s Enhanced frame reception is possible by splitting

the receive queue.

s Modified TAG Mode of operation for easy

conversion from NON-TAG SUPERNET 2 to

SUPERNET 3.

s All SUPERNET 3 registers will be initialized with a

default value on reset.

s The A, C indicator setting has been modified. It is

now possible to control the setting of the A, C

indicators independent of the mode of operation

(online, online special mode, and external

loopback mode).

s Maskable ‘vectored-interrupts’ are provided. It is

now possible to detect the event causing the

interrupt in the SUPERNET 3 in two cycles by

reading the vector register which gives the vector

of the status register followed by a read of the

appropriate status register.

s An additional mode register (MDREG3) is

provided. Setting the bits in this mode register

enables the additional SUPERNET 3 features.

2

SUPERNET 3

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