ADE7880ACPZ-RL 데이터 시트보기 (PDF) - Analog Devices
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ADE7880ACPZ-RL Datasheet PDF : 107 Pages
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ADE7880
Table 4. HSDC Interface Timing Parameter
Parameter
HSA to HSCLK Edge
HSCLK Period
HSCLK Low Pulse Width
HSCLK High Pulse Width
Data Output Valid After HSCLK Edge
Data Output Fall Time
Data Output Rise Time
HSCLK Rise Time
HSCLK Fall Time
HSD Disable After HSA Rising Edge
HSA High After HSCLK Edge
HSA
tSS
Symbol
tSS
tSL
tSH
tDAV
tDF
tDR
tSR
tSF
tDIS
tSFS
Min
0
125
50
50
5
0
tSFS
HSCLK
tSL
tDAV
tSH
tSF
tSR
tDIS
HSD
MSB
INTERMEDIATE BITS
LSB
tDF
tDR
Figure 4. HSDC Interface Timing
2mA
IOL
TO OUTPUT
PIN CL
50pF
800µA
IOH
1.6V
Figure 5. Load Circuit for Timing Specifications
Data Sheet
Max
Unit
ns
ns
ns
ns
40
ns
20
ns
20
ns
10
ns
10
ns
ns
ns
Rev. C | Page 10 of 107
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