AD9674 데이터 시트보기 (PDF) - Analog Devices

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AD9674

Octal Ultrasound Analog Front End

Analog Devices 

Data Sheet

ADC Timing Diagram

N–1

AIN

tA

AD9674

N

tSETUP

TX_TRIG+

tHOLD

TX_TRIG–

tEH

tEL

CLK–

CLK+

DCO–

tCPD

DCO+

FCO–

tFCO

tFRAME

FCO+

DOUTx–

DOUTx+

tPD

tDATA

MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16

Figure 2. 14-Bit Data Serial Stream (Default, RF Decimator Bypassed, Digital HPF Bypassed), One Channel per Lane Mode, FCO Mode = Word

CW Doppler Timing Diagram

MLO–

tMLO

MLO+

RESET–

tSETUP

tHOLD

RESET+

MLO–

Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode

tMLO

MLO+

RESET–

tSETUP

tHOLD

RESET+

Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode

Rev. A | Page 9 of 47

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