AD9674 데이터 시트보기 (PDF) - Analog Devices
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AD9674 Datasheet PDF : 47 Pages
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Data Sheet
AD9674
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), unless
otherwise noted.
Table 2.
Parameter1
INPUTS (CLK+, CLK−, TX_TRIG+, TX_TRIG−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
INPUTS (MLO±, RESET±)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Single-Ended)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO, ADDRx)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 µA)
Logic 0 Voltage (IOL = 50 µA)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (IOL = 50 µA)
Temperature Min
Typ
Max
Unit
Full
CMOS/LVDS/LVPECL
Full
0.2
3.6
V p-p
Full
GND − 0.2
AVDD1 + 0.2 V
Full
0.9
V
25°C
15
kΩ
25°C
4
pF
Full
LVDS/LVPECL
Full
0.250
2 × AVDD2 V p-p
Full
GND − 0.2
AVDD2 + 0.2 V
Full
AVDD2/2
V
25°C
20
kΩ
25°C
1.5
pF
Full
1.2
DRVDD + 0.3 V
Full
0.3
V
25°C
30 (26 for SDIO)
kΩ
25°C
2 (5 for SDIO)
pF
Full
1.2
Full
25°C
26
25°C
2
DRVDD + 0.3 V
0.3
V
kΩ
pF
Full
1.79
V
Full
0.05
V
Full
LVDS
Full
247
454
mV
Full
1.125
1.375
V
Full
Offset binary
Full
LVDS
Full
150
250
mV
Full
1.10
1.30
V
Full
Offset binary
Full
Full
0.05
V
1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. A | Page 7 of 47
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