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AD8158

6.5 Gbps Quad Buffer Mux/Demux

Analog Devices 

LANE DISABLES

By default, the receivers and transmitters enable in an on-demand

fashion according to the state of the SEL[3:0], LB_[A:C], and

BICAST pins or to the state of the equivalent registers in serial

control mode. Register 0x40, Register 0x80, and Register 0xC0

implement per-lane disables for the receivers and Register 0x48,

Register 0x88, and Register 0xC8 implement per-lane transmit-

ter disables. These disables override the default settings. Each

bit in the register is named for the lane and function it disables.

For example, RXDIS B2 disables the receiver on Lane 2 of Port B

while TXDIS C3 disables the Lane 3 transmitter of Port C (see

Table 12).

EQUALIZER SETTINGS

Every input lane offers a low power, asynchronous, programma-

ble receive equalizer for NRZ data up to 6.5 Gbps. The pin

control interface makes four levels of receive equalization

available: 6 dB, 12 dB, 15 dB, and 18 dB. Register-based control

allows the user 10 equalizer settings within this range. High

frequency boost increases monotonically (and approximately

linearly) with EQ control setting in ~2 dB steps.

The four LSBs of Register 0x41, Register 0x81, and Register 0xC1

allow programming of all the equalizers in a port simultane-

ously (see Table 12). The 0x42, 0x43, 0x82, 0x83, 0xC2, and

0xC3 registers allow per-lane programming of the equalizers

(see Table 23). Be aware that writing to the port-level equalizer

registers updates and overwrites per-lane settings.

LOSS OF SIGNAL (LOS)

The serial control interface allows access to the AD8158 loss of

signal features. (LOS is not available in pin control mode.) Each

receiver includes a low power, loss-of-signal detector. The loss-

of-signal circuit monitors the received data stream and

generates a system interrupt when the received signal power

falls below a programmed threshold. The default threshold is

25 mV diff, referred to the input pins. The LOS circuit monitors

the equalized receive waveform and integrates the rms power of

AD8158

the equalized waveform over a selectable interval of either 2 ns

or 10 ns. The detectors are enabled on a per-port basis with Bit 0 of

the RXA/B/C LOS control registers (0x51, 0x91, 0xD1).

By default, when the receiver detects an LOS event, it squelches

its associated transmitter, lowering the output current to

submicroamps. This prevents the high gain, wide bandwidth

signal path from turning low-level system noise on an undriven

input pair into a source of hostile crosstalk at the transmitter.

The squelch feature can be disabled with Bit 3 of the global

squelch control register (0x04).

Register 0x50, Register 0x90, and Register 0xD0 set values for

the LOS signal detection threshold for Port A, Port B, and Port C,

respectively. The recommended setting is Rx LOS threshold

register = 0x10 with Rx LOS control register = 0x05. This is an

optimum setting that all parts are factory tested to comply with

(see Table 1).

LOS Recommended Settings

Rx LOS threshold register: 0x10

Rx LOS control register: 0x05

Register 0x51, Register 0x91, and Register 0xD1 set the integration

interval, LOS gain, and the enable state for the LOS feature for

Port A, Port B, and Port C, respectively (see Table 14 through

Table 16)

Bit 0, LOS_ENB, enables and disables the LOS detectors. (The

default setting is enabled, LOS_ENB = 1).

Bit 1, LOS_GSEL, adjusts the detector gain (1 = high gain, 0 =

low gain). A value of 0 is recommended.

Bit 2, LOS_FILT, adjusts the interval over which incoming data

is averaged. LOS_FILT = 0 gives a 2 ns interval and LOS_FILT = 1

sets a 10 ns interval.

Bit 7 through Bit 3 should be set to 0.

Rev. 0 | Page 19 of 36

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