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AD8158

6.5 Gbps Quad Buffer Mux/Demux

Analog Devices 

AD8158

THEORY OF OPERATION

The AD8158 is a buffered, asynchronous, three-port transceiver

that allows 2:1 multiplexing and 1:2 demultiplexing among its

ports. The 1:2 demux path supports bicast operation, allowing

the AD8158 to operate as a port replicator as well as a redundancy

switch. The AD8158 offers loopback on each lane, allowing the

part to be configured as a 12-lane equalizer or redriver with FFE.

MUX

RXA

RXB

TXC

DEMUX

TXA

RXC

TXB

Figure 35. Mux/Demux Paths, Port A to Port C

The part offers extensively programmable transmit output levels

and pre-emphasis settings as well as squelch or full-disable. The

receivers integrate a programmable, multizero transfer function

for aggressive equalization and a programmable loss-of-signal

feature. The AD8158 provides a balanced, high speed switch

core that maintains low lane-to-lane skew while preserving

edge rates.

The I/O on-chip termination resistors are tied to user-settable

supplies for increased flexibility. The AD8158 supports a wide

primary supply range; VCC can be set from 1.8 V to 3.3 V. These

features, together with programmable transmitter output levels,

allow for a wide range of dc- and ac-coupled I/O configurations.

The AD8158 supports several control and configuration modes,

shown in Table 5.

Table 5. Control Modes

Mode

Description

Toggle Pin

Control

Asynchronous control through toggle pins only

Mixed Control Switch configuration via toggle pins, register-

based control through the I2C serial interface

Serial Control Register-based control through the I2C serial

interface

The pin control mode offers access to a subset of the total

feature list but allows for a much simplified control scheme.

Table 6 compares the available features in all control modes.

The primary advantage of using the serial control interface is

that it allows finer resolution in setting receive equalization,

transmitter pre-emphasis, loss-of-signal (LOS) behavior, and

output levels.

By default, the AD8158 starts in the pin control mode. Strobing

the RESETb pin sets all on-chip registers to their default values

and uses pins to configure switch connectivity, PE, and EQ

levels. In mixed mode, switch connectivity is still controlled

through the SEL[3:0], LB_[A:C], and BICAST pins. The user

can override PE and EQ settings in mixed mode. In serial

mode, all functions are accessed through registers and the

control pin inputs are ignored, except RESETb. Register 0x0F

selects the control mode (see Table 7).

The AD8158 register set is controlled through a 2-wire I2C

interface. The AD8158 acts only as an I2C slave device. The

7-bit slave address for the AD8158 I2C interface contains the

static value b1010 for the upper four bits. The lower three bits

are controlled by the input pins I2C_A[2:0].

Table 6. Features Available Through Toggle Pin or Serial Control

Feature

Pin Control

Switch Features

BICAST

One pin

A/B Lane Select

Four pins

Loopback

Three pins

Rx Features

EQ Levels

Four settings

N/P Swap

Not available

Squelch

Enabled

Tx Features

Programmable Output Levels

±400 mV diff fixed1

PE Levels

Two settings

Serial Control

One bit

Four bits

Three bits

10 settings

Available

Three bits

±200 mV diff/±300 mV diff/±400 mV diff/±600 mV diff

>7 settings

1 ±400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet

both in terms of the differentially measured voltage range (±400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted mV p-p diff. An output

level setting of ±400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.

Rev. 0 | Page 15 of 36

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