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AD7682

16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC

Analog Devices 

AD7682/AD7689

READ/WRITE SPANNING CONVERSION WITH A

BUSY INDICATOR

This mode is used when the AD7682/AD7689 are connected to

any host using an SPI, serial port, or FPGA with an interrupt

input. The connection diagram is shown in Figure 36, and the

corresponding timing is given in Figure 37. For SPI, the host

should use CPHA = CPOL = 1. Reading/writing spanning

conversion is shown, which covers all three modes detailed in

the Digital Interface section.

A rising edge on CNV initiates a conversion, forces SDO to

high impedance, and ignores data present on DIN. After a

conversion is initiated, it continues until completion

irrespective of the state of CNV. CNV must be returned low

before the safe data transfer time, tDATA, and then held low

beyond the conversion time, tCONV, to generate the busy signal

indicator. When the conversion is complete, SDO transitions

from high impedance to low with a pull-up to VIO, which can

be used to interrupt the host to begin data transfer.

After the conversion is complete, the AD7682/AD7689 enter

the acquisition phase and power down. The host must enable

the MSB of CFG at this time (if necessary) to begin the CFG

VIO

AD7682/

AD7689

SDO

CNV

DIN

SCK

update. While CNV is low, both a CFG update and a data

readback take place. The first 14 SCK rising edges are used to

update the CFG, and the first 16 SCK falling edges clock out the

conversion results starting with the MSB. The restriction for

both configuring and reading is that they both occur before the

tDATA time elapses for the next conversion. All 14 bits of

CFG[13:0] must be written or they are ignored. Also, if the 16-bit

conversion result is not read back before tDATA elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an

acceptable hold time. After the optional 17th SCK falling edge,

SDO returns to high impedance. Note that, if the optional SCK

falling edge is not used, the busy feature cannot be detected if

the LSB for the conversion is low.

If CFG readback is enabled, the CFG associated with the

conversion result (n − 1) is read back MSB first following the

LSB of the conversion result. A total of 31 SCK falling edges is

required to return SDO to high impedance if this is enabled.

DIGITAL HOST

MISO

IRQ

SS

MOSI

SCK

tDATA

FOR SPI USE CPHA = 1, CPOL = 1.

Figure 36. Connection Diagram for the AD7682/AD7689 with a Busy Indicator

tCYC

tACQ

tCNVH

tCONV

tDATA

CNV

CONVERSION

(n – 1)

SCK

DIN

SDO

CONVERSION (n – 1)

15

16 17/

31

X

X

X

END CFG (n)

LSB

+1

LSB

END DATA (n – 2)

(QUIET

TIME)

ACQUISITION (n)

CONVERSION (n)

(QUIET ACQUISITION

TIME)

(n + 1)

UPDATE (n)

CFG/SDO

SEE NOTE

UPDATE (n + 1)

CFG/SDO

tDIS

tEN

1

2

tSDItNHDIN

CFG CFG

MSB MSB –1

BEIGN CFG (n + 1)

MSB

MSB

–1

ttHDSSDDOO

BEGIN DATA (n – 1)

15

16

17/

31

tEN

tDIS

X

X

X

END CFG (n + 1)

tDIS

LSB

+1

LSB

END DATA (n – 1) SEE NOTE

tEN

NOTES:

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

Figure 37. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator

Rev. 0 | Page 25 of 28

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