AD7711AR-REEL7 데이터 시트보기 (PDF) - Analog Devices

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AD7711AR-REEL7

LC2MOS Signal Conditioning ADC with RTD Excitation Currents

Analog Devices 

Pin Mnemonic

1 SCLK

2 MCLK IN

3 MCLK OUT

4 A0

5 SYNC

6 MODE

7 AIN1(+)

8 AIN1(–)

9 RTD1

10 RTD2

11 VSS

12 AVDD

13 VBIAS

14 REF IN(–)

15 REF IN(+)

16 REF OUT

17 AIN2

18 AGND

19 TFS

AD7711

PIN FUNCTION DESCRIPTIONS

Function

Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes

active when RFS or TFS goes low, and goes high impedance when either RFS or TFS returns high or when

the device has completed transmission of an output word. When MODE is low, the device is in its external

clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all

2

data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the

information being transmitted to the AD7711 in smaller batches of data.

Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a

CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.

When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

Address Input. With this input low, reading and writing to the device is to the control register. With this input

high, access is to either the data register or the calibration registers.

Logic Input. Allows for synchronization of the digital filters when using a number of AD7711s. It resets

the nodes of the digital filter.

Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its

external clocking mode.

Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source that can be used to check that an external transducer has burned out

or gone open circuit. This output current source can be turned on/off via the control register.

Analog Input Channel 1. Negative input of the programmable gain differential analog input.

Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be

used as the excitation current for RTDs. This current can be turned on or off via the control register.

Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be

used as the excitation current for RTDs. This current can be turned on or off via the control register, and

can be used to eliminate lead resistance errors in 3-wire RTD configurations.

Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1

or AIN2 should not go > 30 mV negative w.r.t. VSS for correct operation of the device.

Analog Positive Supply Voltage, 5 V to 10 V.

Input Bias Voltage. This input voltage should be set such that VBIAS + 0.85 ¥ VREF < AVDD and VBIAS – 0.85

¥ VREF > VSS where VREF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AVDD

and VSS. Thus with AVDD = 5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and

VSS = –5 V, it can be tied to AGND; with AVDD = 10 V, it can be tied to 5 V.

Reference Input. The REF IN(–) can lie anywhere between AVDD and VSS provided REF IN(+) is greater

than REF IN(–).

Reference Input. The reference input is differential provided REF IN(+) is greater than REF IN(–).

REF IN(+) can lie anywhere between AVDD and VSS.

Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output

that is referred to AGND. It is a buffered output capable of providing 1 mA to an external load.

Analog Input Channel 2. Single-ended programmable gain analog input.

Ground Reference Point for Analog Circuitry.

Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial

data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active

after TFS goes low. During a write operation to the AD7711, the SDATA line should not return to high

impedance until after TFS returns high.

REV.G

–7–

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