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AD7711AR-REEL7

LC2MOS Signal Conditioning ADC with RTD Excitation Currents

Analog Devices

AD7711AR-REEL7 Datasheet PDF : 28 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

AD7711–SPECIFICATIONS (AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; VSS = 0 V or –5 V ؎ 5%; REF IN(+) =

+2.5 V; REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.)

Parameter

A, S Versions1

Unit

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Output Noise

Integral Nonlinearity @ 25∞C

TMIN to TMAX

Positive Full-Scale Error2, 3

Full-Scale Drift5

Unipolar Offset Error2

Unipolar Offset Drift5

Bipolar Zero Error2

Bipolar Zero Drift5

Gain Drift

Bipolar Negative Full-Scale Error2 @ 25∞C

TMIN to TMAX

Bipolar Negative Full-Scale Drift5

ANALOG INPUTS/REFERENCE INPUTS

Normal Mode 50 Hz Rejection6

Normal Mode 60 Hz Rejection6

DC Input Leakage Current @ 25∞C6

TMIN to TMAX

Sampling Capacitance6

AIN1/REF IN

Common-Mode Rejection (CMR)

Common-Mode 50 Hz Rejection6

Common-Mode 60 Hz Rejection6

Common-Mode Voltage Range7

Analog Inputs8

Input Voltage Range9

Input Sampling Rate, fS

AIN2 Offset Error

AIN2 Offset Drift

Reference Inputs

REF IN(+) – REF IN(–) Voltage11

Input Sampling Rate, fS

REFERENCE OUTPUT

Output Voltage

Initial Tolerance @ 25∞C

Drift

Output Noise

Line Regulation (AVDD)

Load Regulation

External Current

See Tables I and II

± 0.0015

± 0.003

See Note 4

0.3

See Note 4

0.5

0.25

See Note 4

0.5

0.25

± 0.003

± 0.006

0.3

100

150

VSS to AVDD

0 to +VREF10

± VREF

See Table III

2.5

1.5

+2.5 to +5

fCLK IN/256

2.5

±1

1.5

Bits min

% FSR max

mV/∞C typ

ppm/∞C typ

% FSR max

mV/∞C typ

dB min

pA max

nA max

pF max

dB min

V min to V max

max

mV max

mV/∞C typ

V min to V max

V nom

% max

ppm/∞C typ

mV typ

mV/V max

mV/mA max

mA max

Guaranteed by Design. For Filter Notches £ 60 Hz

For Filter Notch = 100 Hz

For Filter Notch = 250 Hz

For Filter Notch = 500 Hz

For Filter Notch = 1 kHz

Depends on Filter Cutoffs and Selected Gain

Filter Notches £ 60 Hz

Typically ± 0.0003%

Excluding Reference

Excluding Reference. For Gains of 1, 2

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

For Gains of 1, 2

For Gains of 4, 8, 16, 32, 64, 128

For Gains of 1, 2

For Gains of 4, 8, 16, 32, 64, 128

Excluding Reference

Typically ± 0.0006%

Excluding Reference. For Gains of 1, 2

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 ¥ fNOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 ¥ fNOTCH

At DC and AVDD = 5 V

At DC and AVDD = 10 V

For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ¥ fNOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ¥ fNOTCH

For Normal Operation. Depends on Gain Selected

Unipolar Input Range (B/U Bit of Control Register = 1)

Bipolar Input Range (B/U Bit of Control Register = 0)

Removed by System Calibrations but not by Self-Calibration

For Specified Performance. Part Is Functional with

Lower VREF Voltages

Peak-to-Peak Noise. 0.1 Hz to 10 Hz Bandwidth

Maximum Load Current 1 mA

NOTES

1Temperature range is as follows: A Version = – 40∞C to +85∞C; S Version = –55∞C to +125∞C. See also Note 16.

2Applies after calibration at the temperature of interest.

3Positive full-scale error applies to both unipolar and bipolar input ranges.

4These errors will be of the order of the output noise of the part, as shown in Table I, after system calibration. These errors will be 20 mV typical after self-calibration

or background calibration.

5Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

6These numbers are guaranteed by design and/or characterization.

7This common-mode voltage range is allowed, provided the input voltage on AIN(+) and AIN(–) does not exceed AVDD + 30 mV and VSS – 30 mV.

8The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resis-

tance depends on the selected gain (see Tables IV and V).

9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2 input is

with respect to AGND. The absolute voltage on the analog inputs should not go more positive than AVDD + 30 mV, or more negative than VSS – 30 mV.

10VREF = REF IN(+) – REF IN(–).

11The reference input voltage range may be restricted by the input voltage range requirement on the VBIAS input.

–2–

REV. G

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