AD7641ASTRL 데이터 시트보기 (PDF) - Analog Devices

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AD7641ASTRL

18-Bit, 2 MSPS SAR ADC

Analog Devices 

AD7641

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

SYNC to SCLK First Edge Delay Minimum

t18

Internal SCLK Period Minimum

t19

Internal SCLK Period Maximum

t19

Internal SCLK High Minimum

t20

Internal SCLK Low Minimum

t21

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

SCLK Last Edge to SYNC Delay Minimum

t24

BUSY High Width Maximum

t24

0

0

0.5

8

14

2

3

1

0

0

0.630

0

1

3

16

26

6

7

5

0.5

0.5

0.870

1

0

3

32

52

15

16

5

10

9

1.350

1

1

Unit

3

ns

64

ns

103

ns

31

ns

32

ns

5

ns

28

ns

26

ns

2.28

μs

500µA

IOL

TO OUTPUT

PIN CL

50pF

1.4V

500µA

IOH

NOTE

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, CL = 10 pF

0.8V

tDELAY

2V

0.8V

2V

tDELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

Rev. 0 | Page 6 of 28

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