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AD7641ASTRL

18-Bit, 2 MSPS SAR ADC

Analog Devices 

AD7641

SLAVE SERIAL INTERFACE

External Clock

The AD7641 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/INT pin is

held high. In this mode, several methods can be used to read

the data. The external serial clock is gated by CS. When CS and

RD are both low, the data can be read after each conversion or

during the following conversion. The external clock can be

either a continuous or a discontinuous clock. A discontinuous

clock can be either normally high or normally low when

inactive. Figure 38 and Figure 39 show the detailed timing

diagrams of these methods.

While the AD7641 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins

or degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase because the AD7641 provides error correction circuitry

that can correct for an improper bit decision made during

the first half of the conversion phase. For this reason, it is

recommended that when an external clock is being provided,

a discontinuous clock is toggled only when BUSY is low or,

more importantly, that it does not transition during the latter

half of BUSY high.

External Discontinuous Clock Data Read After Conversion

Though the maximum throughput cannot be achieved using

this mode, it is the most recommended of the serial slave

modes. Figure 38 shows the detailed timing diagrams of this

method. After a conversion is complete, indicated by BUSY

returning low, the conversion result can be read while both CS

and RD are low. Data is shifted out MSB first with 18 clock

pulses and is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that conversion

performance is not degraded because there are no voltage

transients on the digital interface during the conversion process.

Another advantage is the ability to read the data at any speed up

to 80 MHz, which accommodates both the slow digital host

interface and the fast serial reading.

Finally, in this mode only, the AD7641 provides a daisy-chain

feature using the RDC/SDIN pin for cascading multiple converters

together. This feature is useful for reducing component count

and wiring connections when desired, as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 37. Simultaneous sampling is possible by using a

common CNVST signal. It should be noted that the RDC/SDIN

input is latched on the edge of SCLK opposite to the one used to

shift out the data on SDOUT. Therefore, the MSB of the

upstream converter just follows the LSB of the downstream

converter on the next SCLK cycle.

BUSY

OUT

BUSY

AD7641

#2

(UPSTREAM)

RDC/SDIN SDOUT

CNVST

CS

SCLK

BUSY

AD7641

#1

(DOWNSTREAM)

RDC/SDIN SDOUT

CNVST

CS

SCLK

DATA

OUT

SCLK IN

CS IN

CNVST IN

Figure 37.Two AD7641 Devices in a Daisy-Chain Configuration

External Clock Data Read During Previous Conversion

Figure 39 shows the detailed timing diagrams of this method.

During a conversion, while CS and RD are both low, the result

of the previous conversion can be read. The data is shifted out,

MSB first, with 16 clock pulses and is valid on both the rising

and falling edge of the clock. The 18 bits have to be read before

the current conversion is complete; otherwise, RDERROR is

pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain

feature in this mode, and the RDC/SDIN input should always

be tied either high or low.

To reduce performance degradation due to digital activity, a fast

discontinuous clock (at least 60 MHz when normal mode is

used, or 80 MHz when warp mode is used) is recommended to

ensure that all the bits are read during the first half of the SAR

conversion phase.

It is also possible to begin to read data after conversion and

continue to read the last bits after a new conversion is initiated.

However, this is not recommended when using the fastest

throughput of any mode because the acquisition time, t8, is

only 115 ns.

If the maximum throughput is not used, thus allowing more

acquisition time, then the use of a slower clock speed can be

used to read the data.

Rev. 0 | Page 24 of 28

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