AD7641ASTRL 데이터 시트보기 (PDF) - Analog Devices

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AD7641ASTRL

18-Bit, 2 MSPS SAR ADC

Analog Devices 

AD7641

CS, RD

t3

CNVST

EXT/INT = 0 RDC/SDIN = 0

INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0

BUSY

SYNC

SCLK

SDOUT

t28

t30

t29

t25

t14

t18

t19

t20

t21

t24

t26

1

2

3

16

17

18

t15

t27

X

D17

D16

D2

D1

D0

t16

t22

t23

Figure 35. Master Serial Data Timing for Reading (Read After Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

t1

t3

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

SYNC

SCLK

t17

t14

t19

t20 t21

t15

1

2

3

t18

t25

t24

t26

16

17

18

t27

SDOUT

X

D17

D16

D2

D1

D0

t16

t22

t23

Figure 36. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

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