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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

AD7621(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD7621
(Rev.:Rev0)
ADI
Analog Devices ADI
AD7621 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD7621
Parameter
Symbol Min
Typ
Max
SLAVE SERIAL INTERFACE MODES5 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time
t31
5
External SCLK Active Edge to SDOUT Delay
t32
1
8
SDIN Setup Time
t33
5
SDIN Hold Time
t34
5
External SCLK Period
t35
12.5
External SCLK High
t36
5
External SCLK Low
t37
5
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface, and RESET sections.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Unit
ns
ns
ns
ns
ns
ns
ns
SERIAL CLOCK TIMING SPECIFICATIONS
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
Symbol
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK High Minimum
t20
Internal SCLK Low Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY High Width Maximum (Wideband and Warp Modes)
t28
BUSY High Width Maximum (Normal Mode)
t28
BUSY High Width Maximum (Impulse Mode)
t28
0
0
1
1
0
1
0
1
Unit
0.5
3
3
3
ns
8
16
32
64
ns
12
25
50
100
ns
2
6
15
31
ns
3
7
16
32
ns
1
5
5
5
ns
0
0.5
10
28
ns
0
0.5
9
26
ns
0.500 0.720 1.160 2.040 μs
0.650 0.870 1.310 2.190 μs
0.780 1.000 1.440 2.320 μs
500μA
IOL
TO OUTPUT
PIN CL
50pF
1.4V
500μA
IOH
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD.
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 32

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