AD7621(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD7621 Datasheet PDF : 32 Pages
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AD7621
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width
Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode)
RESET Pulse Width
RESET Low to BUSY High Delay4
BUSY High Time from RESET Low4
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)
CNVST Low to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay5
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
Symbol Min
Typ
t1
15
t2
333/500/800
t3
t4
t5
1
t6
10
t7
t8
50/70/50
t9
15
t38
10
t39
600
t10
t11
2
t12
t13
2
t14
t15
t16
Max
Unit
701
ns
ns
23
ns
283/430/560 ns
ns
ns
283/430/560 ns
ns
ns
ns
ns
283/430/560 ns
ns
20
ns
15
ns
10
ns
10
ns
10
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period6
Internal SCLK High6
Internal SCLK Low6
SDOUT Valid Setup Time6
SDOUT Valid Hold Time6
SCLK Last Edge to SYNC Delay6
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert6
CNVST Low to SYNC Asserted Delay (All Modes)
SYNC Deasserted to BUSY Low Delay
t17
12/137/263
ns
t18
0.5
ns
t19
8
12
ns
t20
2
ns
t21
3
ns
t22
1
ns
t23
0
ns
t24
0
ns
t25
10
ns
t26
10
ns
t27
10
ns
t28
See Table 4
t29
275/400/500
ns
t30
13
ns
Rev. 0 | Page 5 of 32
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