AD7610 데이터 시트보기 (PDF) - Analog Devices
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AD7610 Datasheet PDF : 32 Pages
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AD7610
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
AGND 3
BYTESWAP 4
OB/2C 5
OGND 6
OGND 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
PIN 1
AD7610
TOP VIEW
(Not to Scale)
36 BIPOLAR
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 TEN
29 BUSY
28 D15/SCCS
27 D14/SCCLK
26 D13/SCIN
25 D12/HW/SW
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 3, 42 AGND
P
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to
AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and
OGND voltages should be at the same potential.
2, 44 AVDD
P
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4
BYTESWAP DI
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on
D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI2
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7, 17 OGND
P
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
8
SER/PAR
DI
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and
the remaining data bits are high impedance outputs.
9, 10 D[0:1]
DO
Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of
SER/PAR.
11, 12 D[2:3] or
DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1]
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data
clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13
D4 or
DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
EXT/INT
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or
external (slave) serial data clock for the AD7610 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
Rev. 0 | Page 8 of 32
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