AD5764 데이터 시트보기 (PDF) - Analog Devices
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AD5764 Datasheet PDF : 27 Pages
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VREFIN
LDAC
16-BIT
DAC
OUTPUT
I/V AMPLIFIER
VOUT
DAC
REGISTER
INPUT
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
Figure 9. Simplified Serial Interface showing input loading
circuitry for one DAC Channel
TRANSFER FUNCTION
Table 6 and Table 7 Show the ideal input code to output voltage
relationship for the AD5744/64 for both Offset binary and twos
complement data coding.
Table 6. Ideal output voltage to input code relationship for the
AD5764
Digital Input
Analog Output
Offset Binary Data Coding
MSB
1111
1000
1111
0000
1111
0000
LSB
1111
0001
1000
0000
0000
0000
0111
1111
1111
1111
0000
0000
0000
0000
Twos Complement Data Coding
MSB
LSB
0111
1111
1111
1111
0000
0000
0000
0001
0000
0000
0000
0000
1111
1000
1111
0000
1111
0000
1111
0000
VOUT
+2 VREF x (32767/32768)
+2 VREF x (1/32768)
0V
-2 VREF x (1/32768)
-2 VREF x (32767/32768)
VOUT
+2 VREF x (32767/32768)
+2 VREF x (1/32768)
0V
-2 VREF x (1/32768)
-2 VREF x (32767/32768)
Preliminary Technical Data
Table 7. Ideal output voltage to input Code relationship for the
AD5744
Digital Input
Analog Output
Offset Binary Data Coding
MSB
11
10
1111
0000
1111
0000
LSB
1111
0001
10 0000
0000
0000
01 1111
1111
1111
00 0000
0000
0000
Twos Complement Data Coding
MSB
LSB
01
1111
1111
1111
00
0000
0000
0001
00
0000
0000
0000
11
1111
10
0000
1111
0000
1111
0000
VOUT
+2 VREF x (8192/8192)
+2 VREF x (1/8192)
0V
-2 VREF x (1/8192)
-2 VREF x (8192/8192)
VOUT
+2 VREF x (8192/8192)
+2 VREF x (1/8192)
0V
-2 VREF x (1/8192)
-2 VREF x (8192/8192)
The output voltage expression for the AD5764 is given by:
VOUT
= −2 ×VREFIN
+
4
×
VREFIN
⎡
⎢⎣
D
65536
⎤
⎥⎦
The output voltage expression for the AD5744 is given by:
VOUT
=
−2 ×VREFIN
+
4
×VREFIN
⎡D
⎢⎣16384
⎤
⎥⎦
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFIN pin.
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low, level sensitive clear that allows the outputs
to be cleared to either 0 V (Offset binary coding) or negative
full scale (twos complement coding). It is necessary to maintain
CLR low for a minimum amount of time (refer to Figure 3) for
the operation to complete. When the CLR signal is returned
high, the output remains at the cleared value until a new value is
programmed. The CLR signal has priority over LDAC and
SYNC. A clear can also be initiated through software by writing
the command 0x04XXXX to the AD5744/64.
Rev. PrA 15-Nov-04| Page 18 of 27
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