AD5764 데이터 시트보기 (PDF) - Analog Devices

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AD5764

Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

Analog Devices 

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5744/AD5764

32

1

SYNC

SCLK

SDIN

SDO

CLR

LDAC

D0

D1

8

9

PIN 1

INDICATOR

AD5744/64

TOP VIEW

(Not to Scale)

25

24

17

16

AGNDA

VOUTA

VOUTB

AGNDB

AGNDC

VOUTC

VOUTD

AGNDD

Figure 6. 32-Lead TQFP Pin Configuration Diagram

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

1

SYNC

2

SCLK13

3

SDIN13

4

SDO

5

CLR13

6

LDAC

7, 8

9

10

11

12

13, 31

14

15, 30

D0, D1

RSTOUT

RSTIN

DGND

DVCC

AVDD

PGND

AVSS

Function

Active Low Input. This is the frame synchronization signal for the serial interface.

While SYNC is low, data is transferred in on the falling edge of SCLK.

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.

This operates at clock speeds up to 30 MHz.

Serial Data Input. Data must be valid on the falling edge of SCLK.

Serial Data Output. Used to clock data from the serial register in daisy-chain or

readback mode.

Active Low Input. Asserting this pin sets the DAC registers to 0x0000.

Load DAC. Logic input. This is used to update the DAC registers and consequently

the analog output. When tied permanently low, the addressed DAC register is

updated on the 24th clock of the serial register write. If LDAC is held high during the

write cycle, the DAC input register is updated but the output is held off until the

falling edge of LDAC. In this mode, all analog outputs can be updated

simultaneously on the falling edge of LDAC.

D0 and D1 form a digital I/O port. The user can configure these pins as inputs or

outputs that are configurable and readable over the serial interface. When

configured as inputs, these pins have weak internal pull-ups to DVCC.

Reset Logic Output. This is the output from the on-chip voltage monitor used in the

reset circuit. If desired, it may be used to control other system components.

Reset Logic Input. This input allows external access to the internal reset logic.

Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation,

RSTIN should be tied to Logic 1.

Digital GND Pin.

Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as

outputs, D0 and D1 are referenced to DVCC.

Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.

Ground Reference Point for Analog Circuitry.

Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.

13 Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.

Rev. PrA 15-Nov-04| Page 11 of 27

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