AD5570BRS(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD5570BRS
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5570BRS Datasheet PDF : 24 Pages
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AD5570
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ,
and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fMAX
t1
t2
t3
t4
Limit at TMIN, TMAX
2
500
200
200
10
Unit
MHz max
ns min
ns min
ns min
ns min
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
t5
35
t6
0
t7
45
ns min
ns min
ns min
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
t8
45
ns min
Minimum SYNC high time
t9
0
ns min
SYNC rising edge to LDAC falling edge
t10
50
ns min
LDAC pulse width
t141
200
ns max
Data delay on SDO
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
SDO; RPULLUP = 5 kΩ, CL = 15 pF.
1 With CL = 0 pF, t15 = 100 ns.
t1
SCLK
t4
t8
t3
t2
t7
SYNC
LDAC1
t10
t9
LDAC2
SDIN
SDO
t6
t5
DB15 (N)
DB0 (N)
DB15
(N+1)
DB15 (N)
DB0
(N+1)
DB0 (N)
t14
DB15
(N+1)
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE
2. SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
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