AD5570BRS(Rev0) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD5570BRS
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5570BRS Datasheet PDF : 24 Pages
| |||
AD5570
STANDALONE TIMING CHARACTERISTICS
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ;
and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN, TMAX
Unit
Description
fMAX
10
MHz max
SCLK frequency
t1
100
ns min
SCLK cycle time
t2
35
ns min
SCLK high time
t3
35
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
35
ns min
Data setup time
t6
0
ns min
Data hold time
t7
45
ns min
SCLK falling edge to SYNC rising edge
t8
45
ns min
Minimum SYNC high time
t9
0
ns min
SYNC rising edge to LDAC falling edge
t10
50
ns min
LDAC pulse width
t11
0
ns min
LDAC falling edge to SYNC falling edge (no update)
t12
0
ns min
LDAC rising edge to SYNC rising edge (no update)
t13
20
ns min
CLR pulse width
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
SCLK
t2
t8
t4
SYNC
SDIN
DB15
t6
t5
LDAC1
t11
LDAC2
t1
t3
t7
DB0
t9
t10
t12
CLR
t13
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 24
Share Link: