AD1987 데이터 시트보기 (PDF) - Analog Devices
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AD1987 Datasheet PDF : 20 Pages
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AD1987
Table 5. AD1987 Pin Descriptions
Mnemonic
Pin No. Function
Description
DIGITAL INTERFACE
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
DIGITAL I/O
GPIO_0
GPIO_1/EAPD
S/PDIF_OUT
JACK SENSE
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
CD_L
CD_GND
CD_R
PORT-B_L
PORT-B_R
PORT-C_L
PORT-C_R
PORT-D_L
PORT-D_R
PORT-A_L
MONO_OUT
PORT-A_R
PORT-G_L
PORT-G_R
PORT-H_L
PORT-H_R
FILTER/REFERENCE
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS-E
VREF_FLT
MIC_BIAS-A
5
I
6
I
8
I/O
10
I
11
I
Link Serial Data Output. Clocked on both edges of BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1987 output stream clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. Master hardware reset.
2
I/O
General-Purpose Input/Output Pin. Digital signal used to control external circuitry.
47
I/O
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
48
O
circuitry. By default pin is in a high-Z state. When used as EAPD: high-Z = amp on,
DVSS = amp off.
S/PDIF_OUT. Supports S/PDIF output.
13
I/O
34
I/O
JACK Sense A-D Input/Sense B Drive.
JACK Sense E-H Input/Sense A Drive.
E 12
LI
Monaural Input From System for Analog PCBeep.
14
LI, MIC, LO, SWAP Auxiliary Input/Output Left Channel.
T 15
LI, MIC, LO, SWAP Auxiliary Input/Output Right Channel.
16
LO
Auxiliary Input/Output Left Channel.
17
LO
Auxiliary Input/Output Right Channel.
18
LI
CD Audio Left Channel.
E 19
LI
CD-Audio-Analog-Ground-Reference (for Differential CD Input). Must be connected
to AGND via 0.1 μF capacitor if not in use as CD_GND.
20
LI
CD Audio Right Channel.
21
LI, MIC, HP, LO Front Panel Stereo MIC/Line-In.
L 22
LI, MIC, HP, LO Front Panel Stereo MIC/Line-In.
23
LI, MIC, LO
Rear Panel Stereo MIC/Line-In.
24
LI, MIC, LO
Rear Panel Stereo MIC/Line-In.
35
LI, HP, LO
Rear Panel Headphone/Line-Out.
O 36
LI, HP, LO
Rear Panel Headphone/Line-Out.
39
LI, MIC, HP, LO Front Panel Headphone/Line-Out.
40
LO
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
41
LI, MIC, HP, LO Front Panel Headphone/Line-Out.
S 43
LO, SWAP
Rear Panel C/LFE Output.
44
LO, SWAP
Rear Panel C/LFE Output.
45
LO
Rear Panel Surround Center/Side.
46
LO
Rear Panel Surround Center/Side.
B 28
O
29
O
31
O
O27
O
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
Voltage Reference Filter.
37
O
Switchable Microphone Bias. For use with Port A (Pins 39, 41)
All MIC_BIAS pins are capable of:
High-Z, 0 V, 1.65 V, 3.78 V, and 3.95 V (with 5.0 V on Pin 33)
DVCORE
1
O
High-Z, 0 V, 1.65 V, 2.86 V, and 3.00 V (with 3.3 V on Pin 33).
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
parallel between Pin 1 and DVSS (Pin 4).
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of driving
headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels (typically used
to support C/LFE or shared C/LFE function).
Rev. A | Page 10 of 20 | March 2008
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