7C132-25 데이터 시트보기 (PDF) - Cypress Semiconductor

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7C132-25

2Kx8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Busy Timing Diagram No. 1 (CE Arbitration)

CEL Valid First:

ADDRESS L,R

ADDRESS MATCH

CEL

CER

BUSYR

tPS

tBLC

tBHC

CER Valid First:

ADDRESSL,R

CER

CEL

BUSYL

ADDRESS MATCH

tPS

tBLC

tBHC

Busy Timing Diagram No. 2 (Address Arbitration)

Left AddressValid First:

ADDRESSL

ADDRESSR

BUSY R

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

Right Address Valid First:

ADDRESS R

ADDRESS L

BUSY L

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

CY7C132/CY7C136

CY7C142/CY7C146

C132-12

C132-13

C132-14

C132-15

9

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