78P7200 데이터 시트보기 (PDF) - TDK Corporation
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78P7200 Datasheet PDF : 11 Pages
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78P7200
E3/DS3/STS-1
Line Interface Unit
RECEIVER (continued)
PARAMETER
Receive clock period
TRCF
Receive clock pulse width TRC
Receive clock positive
transition time
TRCPT
Receive clock negative TRCNT
transition time
Positive or negative TRDP/ TRDN
receive data pulse width
Receive data set-up timeTRDPS/ TRDNS
Receive data hold timeTRDPH/ TRDNH
Receive input jitter tolerance high
frequency (See Note)
Receive input jitter tolerance
low frequency (See Note)
Clock Recovery Phase
KD
Detector Gain
Clock Recovery Phase
KO
Locked Oscillator Gain
CONDITIONS
CL = 15 pF
DS3
STS-1
E3
DS3
STS-1
E3
CL = 15 pF
DS3
STS-1
E3
DS3
STS-1
E3
DS3
STS-1
E3
60 - 300 kHz
DS3
STS-1
10 - 800 kHz
E3
10 - 800 kHz
E3
VIN (min) = ±90 mV, short cable
10 Hz to 2.3 kHz STS-1, DS3
100 Hz to 10 kHz
E3
All 1's data pattern,
DS3
KD = 0.418/RFO
STS-1
E3
MIN
5
5
5
5
0.3
0.15
0.20
10
10
72
12
NOM
22.35
19.29
29.1
12.24
9.65
14.55
4.5
4.5
22.35
19.29
29.1
11.18
9.65
14.55
11.18
9.65
14.55
80
92
62
14.5
Note: UI (Unit Interval) defined as 22.35 ns for DS3, 29.1 ns for E3 and 19.29 ns for STS-1.
MAX
6
UNIT
ns
ns
ns
ns
ns
ns
ns
6
ns
ns
ns
ns
13.7
ns
ns
ns
13.7
ns
ns
ns
UIPP
UIPP
UIPP
UIPP
UIPP
88 µA/Rad
µA/Rad
µA/Rad
17
Mrad/
sec. -Volt
Page: 8 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
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