78P7200 데이터 시트보기 (PDF) - TDK Corporation
부품명
상세내역
일치하는 목록
78P7200 Datasheet PDF : 11 Pages
| |||
TRANSMITTER
The transmitter accepts CMOS logic level clock
(TCLK), positive data (TPOS) and negative data
(TNEG) signals and generates high current drive
pulses on the LOUT+ and LOUT- pins. When
properly connected to a center tapped transformer,
an AMI pulse is generated which can drive a 75Ω
coaxial cable.
Figure 3 shows the timing for the transmitter logic
signals. The output pulse width is internally set and
is not sensitive to input clock (TCLK) pulse width.
When a recommended transformer is used and
option pins are properly set, the transmitted pulse
shape at the end of a 75Ω terminated cable of 0 to
450 feet will fit the template for DSX3 pulse
published in ANSI T1.102-1993, Bellcore
TR-NWT-000499 documents.
For 51.84 Mbit/s STS-1 application the transmitted
pulse for a short cable meets the requirements of
Bellcore GR-253-CORE. For 34 Mbit/s E3
application, the transmitted pulse for a short cable
meets the requirements of ITU-T G.703 when both
LBO and OPT! pins are set LOW.
78P7200
E3/DS3/STS-1
Line Interface Unit
The 78P7200 incorporates a selectable Line
Buildout (LBO) pulse shaper in the transmitter path.
For STS-1 and DS3 applications, the LBO pin
should be set HIGH if the cable is shorter than 225
feet and set LOW for longer cable lengths. For E3
application, LBO pin should be set LOW regardless
of cable length.
The OPT! pin is set HIGH for DS3 and STS-1
operation. The OPT! pin should be set LOW for E3
applications.
The OPT@ pin should be set HIGH for normal
operation. By setting the OPT@ pin to LOW it disables
the transmitter drivers and reduces the power
consumption of the circuit by approximately 125 mW.
Recommended settings for OPT! and LBO pins
SPEED
CABLE
OPT!
LBO
DS3/STS1 < 225'
HI
HI
DS3/STS1 > 225'
HI
LOW
E3
ALL
LOW
LOW
Page: 3 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
Share Link: 