NXP Semiconductors
74LVC594A
8-bit shift register with output register
SHR input
SHCP input
VM
tW
trec
VM
tPHL
Q7S output
VM
mbc324
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the
shift reset to shift clock (SHCP) recovery time
STR input
STCP input
VM
tW
trec
VM
tPHL
Qn outputs
VM
mbc325
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and
the storage reset to storage clock (STCP) recovery time
Table 8. Measurement points
Supply voltage
VCC
VCC < 2.7 V
VCC ≥ 2.7 V
Input
VM
0.5 × VCC
1.5 V
Output
VM
0.5 × VCC
1.5 V
74LVC594A_1
Product data sheet
Rev. 01 — 24 May 2007
© NXP B.V. 2007. All rights reserved.
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