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74LVC594A

8-bit shift register with output register

NXP Semiconductors. 

74LVC594A

8-bit shift register with output register

Rev. 01 — 24 May 2007

Product data sheet

1. General description

The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage

register. Separate clock and reset inputs are provided on both shift and storage registers.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial Power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

The shift register has a serial input (DS) and a serial output (Q7S) for cascading

purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in

the shift register is transferred to the storage register on a positive-going transition of the

STCP input. If both clocks are connected together, the shift register will always be one

clock pulse ahead of the storage register. A LOW level on one of the two register reset

pins (SHR and STR) will clear the corresponding register.

2. Features

s 5 V tolerant inputs/outputs for interfacing with 5 V logic

s Wide supply voltage range from 1.2 V to 3.6 V

s CMOS low-power consumption

s Direct interface with TTL levels

s Balanced propagation delays

s All inputs have Schmitt-trigger action

s Complies with JEDEC standard JESD8-B/JESD36

s ESD protection:

x HBM JESD22-A114-D exceeds 2000 V

x CDM JESD22-C101-C exceeds 1000 V

s Specified from −40 °C to +85 °C and −40 °C to +125 °C.

3. Applications

s Serial-to-parallel data conversion

s Remote control holding register

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