74LVC594A(2017) 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC594A Datasheet PDF : 21 Pages
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74LVC594A
8-bit shift register with output register
Rev. 3 — 20 July 2017
Product data sheet
1 General description
The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register. Separate clock and reset inputs are provided on both shift and storage registers.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a positive-going transition of the
STCP input. If both clocks are connected together, the shift register will always be one
clock pulse ahead of the storage register. A LOW level on one of the two register reset
pins (SHR and STR) will clear the corresponding register.
2 Features and benefits
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low-power consumption
• Direct interface with TTL levels
• Balanced propagation delays
• All inputs have Schmitt-trigger action
• Complies with JEDEC standard:
– JESD8-7A (1.65 V to 1.95 V)
– JESD8-5A (2.3 V to 2.7 V)
– JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM JESD22-A114F exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
3 Applications
• Serial-to-parallel data conversion
• Remote control holding register
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