74LV573 데이터 시트보기 (PDF) - Philips Electronics
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74LV573 Datasheet PDF : 14 Pages
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Philips Semiconductors
Octal D-type transparent latch (3-State)
Product specification
74LV573
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V and v 3.6V
VM = 0.5 * VCC at VCC t 2.7V and w 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V and v 3.6V
VX = VOL + 0.1VCC at VCC < 2.7V and w 4.5V
VY = VOH – 0.3V at VCC w 2.7V and v 3.6V
VY = VOH – 0.1VCC at VCC < 2.7V and w 4.5V
VI
Dn INPUT
VM
GND
tPHL
VOH
tPLH
Qn OUTPUT
VM
VOL
SV00705
Figure 1. Data input (Dn) to output (Qn) propagation delays and
the output transition times
VI
LE INPUT
VM
GND
tW
VOH
tPHL
tPLH
Qn OUTPUT
VM
VOL
SV00706
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Qn) propagation delays and the output
transition times.
VI
OE INPUT
GND
VCC
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VM
tPLZ
VX
tPHZ
tPZL
VM
tPZH
VOH
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VY
outputs
enabled
outputs
disabled
VM
outputs
enabled
SV00664
Figure 3. 3-State enable and disable times
DnINGPUNVTÉÉÉDI ÉÉÉÉÉÉVMÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
th
th
tsu
tsu
VI
LE INPUT
VM
GND
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00665
Figure 4. Data set-up and hold times for the Dn input to the LE
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
VCC
D.U.T.
VO
CL 50 pF
2 * VCC
Open
GND
RL = 1k
RL = 1k
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance.
RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST
S1
VCC
VI
tPLH/tPHL
Open
< 2.7V
VCC
tPLZ/tPZL
tPHZ/tPZH
2 * VCC
GND
2.7–3.6V
w 4.5V
2.7V
VCC
SV00896
Figure 5. Load circuitry for switching times
1998 Jun 10
8
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