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74AHC573 Datasheet PDF : 19 Pages
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NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Input
OE
LE
Dn
Enable and read register (transparent
L
mode)
H
L
H
Latch and read register
L
L
l
h
Latch register and disable outputs
H
L
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
Internal latch
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
VI
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
Tamb = 40 C to +125 C
0.5
0.5
[1] 20
[1] 20
25
-
75
65
[2] -
+7.0 V
+7.0 V
-
mA
+20 mA
+25 mA
+75 mA
-
mA
+150 C
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74AHC_AHCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 25 November 2010
© NXP B.V. 2010. All rights reserved.
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