MAX128ACAI 데이터 시트보기 (PDF) - Maxim Integrated
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MAX128ACAI Datasheet PDF : 16 Pages
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Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
TIMING CHARACTERISTICS (continued)
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; TA = TMIN to TMAX;
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
2-WIRE STANDARD MODE
SCL Clock Frequency
fSCL
100 kHz
Bus Free Time Between a STOP
and START Condition
tBUF
4.7
µs
Hold Time (Repeated) START
Condition
tHD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
tLOW
tHIGH
Setup Time for a Repeated
START Condition
tSU, STA
Data Hold Time
Data Setup Time
tHD, DAT
tSU, DAT
Rise Time for Both SDA and SCL
Signals (Receiving)
tR
4.0
µs
4.7
µs
4.0
µs
4.7
µs
0
0.9
µs
250
ns
1000 ns
Fall Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Transmitting)
Setup Time for STOP Condition
Capacitive Load for Each
Bus Line
Pulse Width of Spike Suppressed
tF
tF
tSU, STO
Cb
tSP
Cb = total capacitance of one bus line in pF,
up to 6mA sink
20 +
0.1 x Cb
4.0
0
300
ns
250
ns
µs
400
pF
50
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-
Supply Rejection test.
External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.
Ground “on” channel, sine wave applied to all “off” channels.
Guaranteed by design. Not tested.
Use static external load during conversion for specified accuracy.
Tested using internal reference.
PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Not subject to production testing. Provided for design guidance only.
6 _______________________________________________________________________________________
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