MAX127ACAI(2012) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX127ACAI Datasheet PDF : 16 Pages
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MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Start a Conversion (Write Cycle)
A conversion cycle begins with the master issuing a
START condition followed by seven address bits (Figure
3) and a write bit (R/W = 0). Once the eighth bit has been
received and the address matches, the MAX127/MAX128
(the slave) issues an acknowledge by pulling SDA low for
one clock cycle (A = 0). The master then writes the input
control byte to the slave (Figure 8). After this byte of data,
the slave issues another acknowledge, pulling SDA low
for one clock cycle. The master ends the write cycle by
issuing a STOP condition (Figure 6).
When the write bit is set (R/W = 0), acquisition starts as
soon as Bit 2 (BIP) of the input control-byte has been
latched and ends when a STOP condition has been
issued. Conversion starts immediately after acquisition.
The MAX127/MAX128’s internal conversion clock fre-
quency is 1.56MHz, resulting in a typical conversion time
of 7.7μs. Figure 9 shows a complete write cycle.
Read a Conversion (Read Cycle)
Once a conversion starts, the master does not need to
wait for the conversion to end before attempting to read
the data from the slave. Data access begins with the mas-
ter issuing a START condition followed by a 7-bit address
(Figure 3) and a read bit (R/W = 1). Once the eighth bit
has been received and the address matches, the slave
issues an acknowledge by pulling low on SDA for one
clock cycle (A = 0) followed by the first byte of serial data
(D11–D4, MSB first). After the first byte has been issued
by the slave, it releases the bus for the master to issue
an acknowledge (A = 0). After receiving the acknowledge,
the slave issues the second byte (D3–D0 and four zeros)
followed by a NOT acknowledge (A=1) from the master to
indicate that the last data byte has been received. Finally,
the master issues a STOP condition (P), ending the read
cycle (Figure 7).
1
7
11
8
11
S SLAVE ADDRESS W A CONTROL-BYTE A P
MASTER TO SLAVE
SLAVE TO MASTER
NO. OF BITS
START CONDITION WRITE
STOP CONDITION
ACKNOWLEDGE ACKNOWLEDGE
Figure 6. Write Cycle
MASTER TO SLAVE
SLAVE TO MASTER
1
7 11
8
18
11
S SLAVE ADDRESS R A DATA-BYTE A DATA-BYTE A P
NO. OF BITS
ACKNOWLEDGE
START CONDITION READ
STOP CONDITION
NOT ACKNOWLEDGE
Figure 7. Read Cycle
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 ACK
SDA
MSB
LSB
SCL
START: FIRST LOGIC “1” RECEIVED AFTER ACKNOWLEDGE OF A WRITE.
ACK: ACKNOWLEDGE BIT. THE MAX127/MAX128 PULL SDA LOW DURING THE
9TH CLOCK PULSE.
Figure 8. Command Byte
SLAVE ADDRESS BYTE
0
1
SDA
MSB
W
A
LSB
SCL
1
2
7
8
9
A/D STATE
START
CONDITION
CONTROL BYTE
S
MSB
10 11
BIP PD1 PD0 A
LSB
15 16 17 18
ACQUISITION
CONVERSION
STOP
CONDITION
Figure 9. Complete 2-Wire Serial Write Transmission
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