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P3041

P3041 QorIQ Integrated Processor Hardware Specifications

Freescale Semiconductor 

Pin Assignments and Reset States

LAD21

LAD22

LAD23

LAD24

LAD25

LAD26

LAD27

LAD28

LAD29

LAD30

LAD31

LDP0

LDP1

LDP2

LDP3

LA27

LA28

LA29

LA30

LA31

LCS0

LCS1

LCS2

LCS3

LCS4

LCS5

LCS6

LCS7

LWE0

LWE1

LWE2

LWE3

LBCTL

LALE

Signal

Table 1. Pins List by Bus (continued)

Signal Description

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Muxed data/address

Data parity

Data parity

Data parity

Data parity

Non-muxed address

Non-muxed address

Non-muxed Address

Non-muxed Address

Non-muxed Address

Chip selects

Chip selects

Chip selects

Chip selects

Chip selects

Chip selects

Chip selects

Chip selects

Write enable

Write enable

Write enable

Write enable

Buffer control

Address latch enable

Package Pin

Pin Number Type

E21

I/O

F21

I/O

H21

I/O

K21

I/O

G20

I/O

J20

I/O

D26

I/O

E18

I/O

F18

I/O

J15

I/O

F17

I/O

J24

I/O

K23

I/O

H17

I/O

H16

I/O

K20

O

G19

O

H19

O

J19

O

G18

O

D19

O

D20

O

E20

O

D21

O

D22

O

B23

O

F24

O

G26

O

D24

O

A24

O

J16

O

K15

O

C22

O

A23

I/O

Power

Supply

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

BVDD

Notes

35

35

3

3

35

3,32

—

—

—

—

—

—

—

—

—

—

35

35

35

35

5

5

5

5

5

5

5

5

—

—

—

—

—

—

P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2

14

Freescale Semiconductor

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