TC58DVM72A1F 데이터 시트보기 (PDF) - Toshiba

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TC58DVM72A1F

128-MBIT (16M u8 BITS/8M x 16BITS) CMOS NAND E²PROM

Toshiba 

TC58DVM72A1FT00/ TC58DVM72F1FT00

TC58DAM72A1FT00/ TC58DAM72F1FT00

Schematic Cell Layout and Address Assignment

The Program operation works on page units while the Erase operation works on block units.

512

16

I/O1

I/O8

A page consists of 528 bytes in which 512 bytes are used

for main memory storage and 16 bytes are for redundancy

or for other uses.

32768 pages

1024 blocks

32 pages

1 block

1 page 528 bytes

1 block 528 bytes u 32 pages (16K  512) bytes

Capacity 528 bytes u 32 pages u 1024 blocks

8I/O

528

Figure 2. Schematic Cell Layout

256

8

I/O1

I/O16

32768 pages

1024 blocks

32 pages

1 block

16I/O

264

Figure 2-2. x16 Schematic Cell Layout

A page consists of 264 words in which 256 words are

used for main memory storage and 8 words are for

redundancy or for other uses.

1 page 264 words

1 block 264 words u 32 pages (8K  256) words

Capacity 264 words u 32 pages u 1024 blocks

An address is read in via the I/O port over three

consecutive clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

First cycle

A7 A6 A5 A4 A3 A2 A1 A0

Second cycle

A16 A15 A14 A13 A12 A11 A10 A9

Third cycle

*L A23 A22 A21 A20 A19 A18 A17

*: A8 is automatically set to Low or High by a 00H command or a 01H command.

I/O9-16 should be low when address is input.

* I/O8 must be set to Low in the third cycle.

A0~A7: Column address

A9~A23: Page address

A14~A23: Block address

A9~A13: NAND address in block

2003-01-24 17/34

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