MAX1907A 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1907A

Quick-PWM Master Controllers for Voltage Positioned CPU Core Power Supplies (IMVP-IV)

Maxim Integrated 

Quick-PWM Master Controllers for Voltage-

Positioned CPU Core Power Supplies (IMVP-IV)

Pin Description (continued)

PIN

19

20

21–26

NAME

CSN

DPSLP

FUNCTION

Negative Current-Limit Input. Connect to the negative terminal of the current-sense resistor.

Deep-Sleep Control Input. When DPSLP is low the system enters the deep-sleep state and the regulator

applies the appropriate deep-sleep offset. The MAX1907A/MAX1981A adds the offset measured at the POS

and NEG pins to the output. 32 clock cycles after the deep-sleep transition is completed, DDO goes low

(see the Driver Disable and Low-Power Pulse Skipping section). Another 32 clock cycles later, the

MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.

D5–D0

Low-Voltage VID DAC Code Inputs. D0 is the LSB, and D5 is the MSB of the internal 6-bit VID DAC (Table

4). The D0–D5 inputs do not have internal pullups. These 1V logic inputs are designed to interface directly

with the CPU. In all normal active modes (modes other than suspend and boot), the output voltage is set by

the VID code indicated by the D0–D5 logic-level voltages on D0–D5. In suspend mode (SUS = high), the

decoded state of the four-level S0–S2 inputs sets the output voltage. In boot mode (see the Power-Up

Sequence section), the decoded state of the four-level B0–B2 inputs set the output voltage.

Driver-Disable Output. This TTL-logic output can be used to disable the driver outputs on slave-switching

regulator controllers. This forces a high-impedance condition and makes it possible for the

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DDO MAX1907A/MAX1981A master controller to operate in low current SKIP mode. DDO goes low 32 RTIME

clock cycles after the MAX1907A/MAX1981A completes a transition to the suspend mode or deep-sleep

voltage (see the Driver Disable and Low-Power Pulse Skipping section). Another 30 clock cycles later, the

MAX1907A/MAX1981A enters automatic pulse-skipping operation.

28

PGND Power Ground. Ground connection for the DL gate driver.

Low-Side Gate Driver Output. DL swings from PGND to VDD. DL is forced high after the

29

DL MAX1907A/MAX1981A powers down (SHDN = GND) or when the controller detects a fault. The MAX1981A

does not include overvoltage protection.

30

VDD

Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (4.5V to 5.5V). Bypass to

PGND with a 1µF or greater ceramic capacitor, as close to the IC as possible.

31

BST Boost Flying Capacitor Connection. An optional resistor in series with BST allows the DH pullup current to

be adjusted.

32

LX

Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It connects to the

skip-mode zero-crossing comparator.

33

DH High-Side Gate Driver. Output swings LX to BST.

34

V+

Battery Voltage Sense Connection. Used only for PWM one-shot timing. DH on-time is inversely proportional

to input voltage over a range of 2V to 28V.

Suspend-Mode Control Input. When SUS is high the regulator slews to the suspend voltage level. This level

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SUS

is set with four-level logic signals at the S0–S2 inputs. 32 clock cycles after the transition to the suspend-

mode voltage is completed, DDO goes low (see the Driver Disable and Low-Power Pulse Skipping section).

Another 32 clock cycles later, the MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.

System Power-Good Input. Primarily, SYSPOK serves as the wired NOR junction of the open-drain power-

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SYSPOK

good signals for the VCCP and VCCMCH supplies. A falling edge on SYSPOK shuts down the

MAX1907A/MAX1981A and sets the fault latch. Toggle SHDN or cycle VCC power below 1V to restart the

controller.

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