MAX1907A 데이터 시트보기 (PDF) - Maxim Integrated
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MAX1907A
Maxim Integrated
MAX1907A Datasheet PDF : 43 Pages
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Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
PIN
1, 2, 3
4, 5, 6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Description
NAME
B0–B2
FUNCTION
Boot-Mode Voltage Select Inputs. B0–B2 are four-level digital inputs that select the boot-mode VID code
(Table 6) for the boot-mode multiplexer inputs. During power-up, the boot-mode VID code is delivered to
the DAC (see the Internal Multiplexers section).
S0–S2
SHDN
REF
Suspend-Mode Voltage Select Inputs. S0–S2 are four-level digital inputs that select the suspend-mode VID
code (Table 5) for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID code is
delivered to the DAC (see the Internal Multiplexers section).
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal
operation. Connect to ground to put the IC into its 10µA (max) shutdown state. During the transition from
normal operation to shutdown the output voltage is ramped down at the output voltage slew rate
programmed by the TIME pin. In shutdown mode, DL is forced to VDD to clamp the output to ground.
Forcing SHDN to 12V~15V disables both overvoltage protection and undervoltage protection circuits, and
clears the fault latch. Do not connect SHDN to >15V.
2V Reference Output. Bypass to GND with 0.22µF or greater ceramic capacitor. The reference can source
50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load
regulation error.
ILIM
VCC
GND
CC
POS
Current-Limit Adjustment. The current-limit threshold defaults to 50mV if ILIM is tied to VCC. In adjustable
mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM over a 100mV to 1.5V
range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V.
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a
series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC as possible.
Analog Ground
Integrator Capacitor Connection. Connect a 47pF to 1000pF (270pF typ) capacitor from CC to GND to set
the integration time constant.
Feedback Offset Adjust Positive Input. The output shifts by 100% (typ) of the differential input voltage
appearing between POS and NEG when DPSLP is low. The common-mode range of POS and NEG is 0 to
2V. POS and NEG should be generated from resistor dividers from the output.
NEG
Feedback Offset Adjust Negative Input. The output shifts by 100% (typ) of differential input voltage
appearing between POS and NEG when DPSLP is low. The common-mode range of POS and NEG is 0 to
2V. POS and NEG should be generated from resistor dividers from the output.
Feedback Input. FB is internally connected to both the feedback input and the output of the voltage-
FB positioning op amp (Figure 2). Connect a resistor between FB and OAIN- (Figure 1) to set the voltage-
positioning gain (see the Setting Voltage Positioning section).
OAIN-
OAIN+
CSP
Dual-Mode Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for
additional voltage-positioning gain (Figure 1), connect to the negative terminal of current-sense resistor
through a 1kΩ ±1% resistor as described in the Setting Voltage Positioning section. Connect OAIN- to VCC
to disable op amp. The logic threshold to disable the op amp is approximately VCC - 1V.
Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain (Figure 1),
connect to the positive terminal of current-sense resistor through a resistor as described in the Setting Voltage
Positioning section.
Positive Current-Limit Input. Connect to the positive terminal of the current-sense resistor.
14 ______________________________________________________________________________________
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