CY7C1485V33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1485V33 Datasheet PDF : 26 Pages
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CY7C1484V33
CY7C1485V33
Pin Definitions
Pin Name
A0, A1, A
BWA, BWB
BWC, BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
VDD
VSS
VSSQ[2]
VDDQ
IO
Description
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.
A1: A0 are fed to the two-bit counter.
Input-
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
Synchronous SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
Input-
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must
Synchronous be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
Input-
Asynchronous
Output Enable, Asynchronous Input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Input-
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Synchronous
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-
Asynchronous
ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.
IO-
Synchronous
Power Supply
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by the addresses presented during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
IO Ground Ground for the IO circuitry.
IO Power Supply Power supply for the IO circuitry.
Note
2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
Document #: 38-05285 Rev. *G
Page 5 of 26
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