CY7C1485V33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1485V33 Datasheet PDF : 26 Pages
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CY7C1484V33
CY7C1485V33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1484V33/CY7C1485V33 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not
have the set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
The CY7C1484V33/CY7C1485V33 contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. TDO should be
left unconnected. At power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
TAP Controller State Diagram
1 TEST-LOGIC
RESET
0
0 RUN-TEST/ 1
IDLE
SELECT
1
DR -SCA N
0
1
CA PTU R E-DR
0
SHIFT-DR 0
1
1
EXIT1-DR
0
PAUSE-DR 0
1
0
EXIT2-DR
1
U PDA TE-DR
10
SELECT
1
IR -SCA N
0
1
CA PTU R E-IR
0
SHIFT-IR
0
1
1
EXIT1-IR
0
PAUSE-IR 0
1
0
EXIT2-IR
1
U PDA TE-IR
10
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and
can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction
that is loaded into the TAP instruction register. For information
about loading the instruction register, see the TAP Controller
State Diagram. TDI is internally pulled up and can be uncon-
nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSB) of any register. (See TAP
Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
Whether the output is active depends upon the current state
of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit
(LSB) of any register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
210
Selection
TDI
Circuitry
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 210
Boundary Scan Register
TCK
TAP CONTROLLER
TMS
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Document #: 38-05285 Rev. *G
Page 10 of 26
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