MK5027(2003) 데이터 시트보기 (PDF) - STMicroelectronics
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MK5027 Datasheet PDF : 19 Pages
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MK5027
AC TIMING SPECIFICATIONS (Continued)
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
No Signal Symbol
Parameter
Test
Conditions
13 RCLK
TRCT RCLK period
14 RCLK TRCH RCLK high time
15 RCLK TRCL RCLK low time
16 RCLK TRCR Rise time of RCLK
17 RCLK TRCF Fall time of RCLK
18 RD
TRDR RD data rise time
19 RD
TRDF RD data fall time
20 RD
TRDH
RD hold time after rising edge of
RCLK
21 RD
TRDS RD setup time prior to rising edge of
RCLK
22 A/DAL
TDOFF Bus Master driver disable after rising
edge of HOLD
23 A/DAL
TDON Bus Master driver enable after falling TSCT = 100ns
edge of HLDA
24 HLDA
THHA Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
25 RESET TRW RESET pulse width
26 A/DAL
27 A
TCYCLE
TXAS
Read/write, address/data Cycle Time TSCT = 100ns
Address setup time to falling edge
of ALE
28 A
TXAH
Address hold time after the rising
edge of DAS
29 DAL
TAS Address setup time to falling edge
of ALE
30 DAL
TAH Address hold time after the falling
edge of ALE
31 DAL
TRDAS Data setup time to the falling edge
of DAS (Bus Master read)
32 DAL
TRDAH Data hold time after the rising edge
of DAS (bus master read)
33 DAL
TDDAS Data setup time to the falling edge of
DAS (bus master write)
34 DAL
TWDS Data setup time to the rising edge of
DAS (bus master write)
35 DAL
TWDH Data hold time to the rising edge of
DAS (bus slave write)
36 DAL
TSRDH Data hold time after the rising edge
of DAS (bus slave read)
TSCT = 100ns
37 DAL
TSWDH Data hold time after the rising edge
of DAS (bus slave write)
38 DAL
TSWDS Data setup time to the falling edge of
DAS (bus slave write)
39 ALE
TALEW ALE width high
40 ALE
TDSW Delay from rising edge od DAS to
the rising edge of ALE
41 DAS
TDSW DAS width low
Min.
140
63
63
0
0
0
0
5
30
0
0
0
30
600
100
50
75
20
55
0
0
250
35
0
0
0
110
70
200
Typ.
Max.
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
ns
ns
ns
ns
11/19
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